The present invention relates to a method for fabricating a semiconductor, especially a vertical type static induction transistor(SIT) or FET having a structure provided with a first region of high impurity density(e.g., gate region) encircling a second region of high impurity density(e.g., source or drain region).
To explain the problems or limitations of the conventional fabricating method, a SIT in a SITL having a lateral bipolar transistor as load is illustrated as an example of the above-mentioned semiconductor device in FIG. 1.
FIG. 1(a) is a plane view of a SITL of the so-called planar-gate type. Upward type SIT and oxide films are omitted thereform to simplify the figure. FIG. 1(b) is a sectional view taken on the line A--A' in FIG. 1(a). A lateral p n p bipolar transistor for a load is composed of p.sup.+ emitter(injector) region 15, n.sup.- base(epitaxial) region 13 and p.sup.+ collector(gate) region 14. An upward type SIT is composed of the P.sup.+ gate region 14, which corresponds to the first region encircling n.sup.+ drain region 11 which corresponds to the second region, n.sup.- channel(epitaxial) region 13 and n.sup.+ source region 12 between substrates. A drain electrode 1 is connected to the n.sup.+ drain region 11 through a window 111 for drain contact and a gate electrode 4 is connected to p.sup.+ gate region 14 through a window 114 for gate contact. An injector electrode 5 is connected to a p.sup.+ injector region 15 through a window 115 for injector contact, and n.sup.+ source region 12 is normally grounded.
Such a structure will be normally fabricated by the following method. At first, an n.sup.- epitaxial growth layer 13 is formed on the substrate including also n.sup.+ source region 12 or buried layer, and then, the p.sup.+ injector region 15 and the p.sup.+ gate region 14 are formed by oxidation, photo-lithography and selective diffusion. For high speed operation and lower power consumption, a small area of p.sup.+ gate region 14 and a window for diffusion with small line width(first window) are usually required. However, it is difficult to obtain good reproducibility by today's photo-lithography technique when the width is less than a few .mu.m, and more typically, less than about 2 .mu.m. The window with a width of less than 1 .mu.m can be obtained by an electron beam exposure, however, it is not suitable for mass production. Next, although a window for forming n.sup.+ drain region 11(a second window) is defined so as to be encircled by the p.sup.+ gate region 14, in order to reduce the capacitance between the gate-drain, the formation of a small window and high accuracy in positioning are required. These requirements become more severe as the width of n.sup.+ channel region 13(gate space) inside of p.sup.+ gate region 14 becomes narrow. The gate space depends upon the impurity density of n.sup.+ channel region 13 and the requirement for SIT characteristics and the value is normally selected to be less than 10 .mu.m. Particularly, to reduce the value of leakage current when the gate voltage is zero, severe fabrication accuracy will be required since the gate space is normally selected to be less than 5 .mu.m. Next, the windows for electrodes 111, 114 and 115 are defined and metal evaporation, such as Al, and photo-lithography are carried out to obtain a complete device.
As described above, when precise fabrication is required for a SIT for increasing the performance of an IC and integration density, the requirements for accuracy of line width or positioning at the fabrication of the gate region window and the drain region window become more severe for the photo-lithography technique. The accuracy limitation for today's technology will be about 2 .mu.m in line width and range between 0.5 and 1 .mu.m in positioning. The limitation of the performance depends upon these accuracy limitations. There is a similar problem to that of SITL in a vertical-type SIT, a vertical-type FET, high impurity density region (graft base) for emitter(or collector) and base electrodes of a bipolar transistor and a short channel MOS transistor.
The present invention is intended to remove these problems in the conventional manufacturing method and to provide a method for fabricating semiconductor devices mentioned above, wherein precise fabrication and high accuracy positioning can be realized even by today's photo-lithography technique without increasing the number of masking steps.
An object of the present invention is to provide a fabricating method in which multi-insulation layered structure composed of oxide film and nitride film is employed and side etching for these insulation films is actively utilized.
Another object of the present invention is to provide a method for effectively controlling the amount removed by side etching.